1. Field of the Invention
The present invention relates generally to methods and circuits for biasing one or more transconducting cells to operate in a subthreshold state so as to have a desired high transconductance, and to systems including one or more transconducting cells biased in accordance with the invention to operate in subthreshold. More specifically, the invention relates to methods and circuits for biasing at least one transconducting cell to operate in subthreshold by setting the current density for at least one transistor of each cell such that the current density remains fixed (at a level at which the transistor operates in or near subthreshold) despite significant supply voltage variations, and to systems including at least one so-biased transconducting cell.
2. Description of the Related Art
Throughout the disclosure, including in the claims, the term "transconductance" (denoted by the symbol "g.sub.m ") denotes the change in channel current of a transistor, in response to a change in gate-to-source voltage V.sub.GS (for a MOSFET transistor) or in response to a change in base-to-emitter voltage V.sub.BE (for a bipolar transistor). Throughout the disclosure, including in the claims, the term "transconducting cell" denotes a circuit that comprises one or more transistors, is characterized by a transconductance (determined by the transconductance of each of said one or more transistors and, if there are more than one of said one or more transistors, by the manner in which said transistors are connected together), is operable in or near a subthreshold state in which the transconductance has a desired value, and has an output voltage determined by an input voltage. Typically, the invention is employed to bias an "inverting" transconducting cell whose output voltage decreases in response to increasing input voltage (and whose output voltage increases in response to decreasing input voltage).
A metal-oxide-semiconductor field-effect transistor ("MOSFET" or "MOS" transistor) has a "gate" terminal which capacitively modulates the conductance of a surface channel which joins two end contacts, known as a source and a drain. The gate is separated from a semiconductor body which underlies the gate by a thin gate insulator. This gate insulator is usually composed of silicon dioxide. The channel is formed at the interface between the semiconductor body and the gate insulator.
Although there are devices known as depletionmode (normally on) MOSFETs, the term MOSFET is usually used to denote an enhancement-mode (normally off) device. The latter device is normally off because the body forms p-n junctions with both the source and the drain, so that no majority-carrier current can flow between the source and drain. Instead, minority-carrier current can flow, but only if minority carriers are available. For gate biases that are sufficiently attractive (i.e., above a threshold voltage), minority carriers are drawn into a surface channel, forming a conducting path from source to drain. Threshold voltage is often defined as the gate-to-source voltage V.sub.GS =V.sub.th at which the channel begins to form (a more precise definition of threshold voltage will be discussed below with reference to FIG. 5). The gate and channel form two sides of a capacitor separated by the gate insulator. As additional attractive charges are placed on the gate side, the channel side of the capacitor draws a balancing charge of minority carriers from the source and the drain. With increasing charge on the gate, the channel is more populated, and the conductance increases. Because the gate creates the channel, to insure electrical continuity, the gate usually extends over the entire length of the separation between the source and the drain.
When the gate-to-source voltage of an N-channel MOSFET ("NMOS" transistor) rises to the threshold voltage V.sub.th, the NMOS transistor begins to switch from off to on. When the gate-to-source voltage of a P-channel MOSFET ("PMOS" transistor) falls below the threshold voltage v.sub.th, the PMOS transistor begins to switch from off to on. Above the threshold voltage, an NMOS transistor develops an excess of gate voltage beyond that required to "invert" the polarity of the carriers at the surface of the semiconductor. It is useful to think of this quantity, V.sub.GS -V.sub.th as V.sub.Gth, which has a "positive" value for an NMOS transistor and a corresponding "negative" value for a PMOS transistor.
The resulting NMOS (or PMOS) drain current than depends on both V.sub.Gth and the drain-to-source voltage, "V.sub.ds ". For an NMOS transistor, when
V.sub.ds &lt;&lt;V.sub.Gth ("-V.sub.ds &lt;&lt;-V.sub.Gth " for a PMOS transistor,) the device is said to operate in the "linear" region; and when PA1 V.sub.ds .gtoreq.V.sub.Gth ("-V.sub.ds .gtoreq.-V.sub.Gth " for a PMOS transistor, the device is said to operate in the "saturation" region; and when PA1 .alpha.V.sub.Gth .ltoreq.V.sub.ds .ltoreq.V.sub.Gth ("-.alpha.V.sub.Gth .ltoreq.-V.sub.ds .ltoreq.-V.sub.Gth " for a PMOS transistor,) where a is a constant less than one (typically 0.1-0.25), the device is said to operate in the "triode" region. PA1 .phi..sub.b .gtoreq..phi..sub.s .gtoreq.-.phi..sub.b (".phi..sub.b .gtoreq.-.phi..sub.s .gtoreq.-.phi..sub.b " for a PMOS transistor.) PA1 .phi..sub.s =.phi..sub.b, the semiconductor surface is neutral, i.e. neither accumulated nor depleted, and V.sub.GS is equal to the so-called flat-band voltage, "V.sub.FB "; and when PA1 .phi..sub.s =-.phi..sub.b, the semiconductor surface is at the onset of so called strong inversion and V.sub.Gth =0 (because of aforesaid definition of V.sub.th); and when PA1 .linevert split..phi..sub.b .linevert split..gtoreq.-.linevert split..phi..sub.b .linevert split., the semiconductor surface goes from partial depletion through intrinsic and into weak inversion before attaining strong inversion. PA1 the number of carriers in the channel is so small that their charge does not significantly affect the channel potential, and the channel carriers simply adapt to the potential set up between drain and source and to the space charge caused by depleted dopant ions in the channel. PA1 a subthreshold minority charge component, "Q'.sub.n " for an NMOS device ("Q'.sub.p " for a PMOS) which will subsequently be shown to vary exponentially with V.sub.GS ; and, PA1 a strong inversion majority charge component, "Q.sub.n " for an NMOS device, ("Q.sub.p " for a PMOS device) which will subsequently be shown to vary linearly with V.sub.Gth and, therefor V.sub.GS. Thus, Q.sub.ch (V.sub.GS)=Q'.sub.n +Q.sub.n for an NMOS device and Q.sub.ch (V.sub.GS)=Q'.sub.p +Q.sub.p for a PMOS device. PA1 the subthreshold charge can be approximated as ##EQU1## for NMOS devices and as ##EQU2## for PMOS devices, where "k" is the so called Boltzmann constant, "q"" is the electronic charge, "Na" is the acceptor dopant concentration in the channel of the NMOS device, "Nd" is the donor dopant concentration in the channel of the PMOS device, ".epsilon..sub.si " is the permittivity of silicon, "V.sub.d " is the drain-to-source voltage in the linear and triode regions but is limited to V.sub.d =V.sub.Gth ="V.sub.ds-sat " in the saturation region; and, PA1 the strong inversion charge can be approximated as ##EQU3## for NMOS devices and as ##EQU4## for a PMOS devices, where "W" and "L" are the width and length of the channel, respectively, C'.sub.ox is the effective area gate capacitance, and "V.sub.d " is the drain-to-source voltage in the linear and triode but is limited to V.sub.d =V.sub.Gth ="V.sub.ds-sat " when operating in the saturation region where it is assumed that V.sub.Gth .gtoreq.0 for an NMOS device and V.sub.Gth .ltoreq.0 for a PMOS device. PA1 a minority carrier current component, "I.sub.ds-minor ", which is now proportional to V.sub.d exp q(V.sub.Gth -V.sub.d /2)/kT! in the linear and triode drain-bias regions and proportional to V.sub.ds-sat exp q(V.sub.Gth -V.sub.ds-sat /2)/kT! or, simplifying, V.sub.Gth exp q(V.sub.Gth)/2kT! in the saturation region; and PA1 a majority carrier current component, "I.sub.ds-major ", which is now proportional to V.sub.d (V.sub.Gth -V.sub.d /2) in the linear and triode drain-bias regions and proportional to V.sub.ds-sat (V.sub.Gth -V.sub.ds-sat /2) or, simplifying, V.sub.Gth.sup.2 /2 in the saturation drain-bias region.
Additionally, above the threshold voltage, an NMOS transistor (below the threshold voltage, a PMOS transistor) exhibits drain current versus gate bias characteristics which are dependent upon whether the MOSFET is a long-channel device or is a short-channel device. For a long-channel device, the current in saturation increases proportionally to the square of the gate bias. For short channel devices, the drain current exhibits a somewhat more linear increase in saturation current with gate bias.
Notwithstanding the relationships defined herein between V.sub.ds and V.sub.Gth, and the resulting three "drain-bias" operating regions relating these quantities, and, notwithstanding certain non-idealities associated with said short-channel effects, an NMOS transistor is said to be operating "in subthreshold" whenever the value of V.sub.GS results in a relationship between the surface potential, ".phi..sub.s ", and the built-in potential, ".phi..sub.b ", such that
Additionally, within this range for .phi..sub.s, for either an NMOS or PMOS transistor, when
Within said subthreshold region,
When the mobile carriers are less numerous than the dopant ions, they are known as "minority" carriers. When the mobile carriers are more numerous than the dopant ions (which occurs for the first time at the strong inversion threshold, V.sub.Gth =0,) they become known as "majority" carriers. In either case, the carriers remain of the same nature (electrons for NMOS devices and holes for PMOS devices) and contribute to current flow by drift and diffusion mechanisms. The practice of designating the carriers as minority and majority serve the purpose of segregating the relationship of channel-charge to gate bias, "Q.sub.ch (V.sub.GS)", into two categories:
For long-channel devices operating within the linear, triode or saturation regions, it can be shown that:
It can be observed from the above expressions describing channel charge that the minority channel charge is exponentially dependant on V.sub.GS over all three drain-bias regions whereas the majority channel charge is only linearly dependant on V.sub.Gth, and therefor V.sub.GS, over all three drain-bias regions.
The drain current that results from the total charge in the channel is merely ##EQU5## where ".tau..sub.tr " is the average time for a carrier to transit the channel. For an NMOS device, .tau..sub.tr =L.sup.2 /.mu..sub.n V.sub.d, and, for a PMOS device, .tau..sub.tr =L.sup.2 /.mu..sub.p V.sub.d, where ".mu..sub.n " and ".mu..sub.p " are the effective mobility for electrons and holes, respectively, and I.sub.ds can be restated as ##EQU6## where ".mu..sub.n,p " is .mu..sub.n for NMOS devices and .mu..sub.p for PMOS devices.
Because I.sub.ds is now proportional to V.sub.d for a fixed value of Q.sub.ch, the effect of this factor, combined with the aforementioned dependance of both Q'.sub.n and Q.sub.n in NMOS devices (and Q'.sub.p and Q.sub.p in PMOS devices) on V.sub.d, results in I.sub.ds having two components:
For short-channel devices, however, the source and drain are sufficiently close to each other to begin to share control of V.sub.th. If this effect is too strong, a drain voltage dependence of the subthreshold characteristic, as well as the strong inversion characteristic, then occurs, which at least in switching applications, is undesirable because such condition increases the MOSFET off current and can cause a drain-bias dependent threshold voltage.
For a well-designed MOSFET V.sub.th does not depend significantly on the drain and the channel current characteristics remain substantially as described.
FIG. 5 is a graph of the square root of the channel current (i.e., the square root of the current "I.sub.ds " at the transistor's drain) of a typical NMOS transistor whose drain and gate are connected together (and therefor operating in the saturation drain-bias region) plotted on the "y" axis, versus the gate-to-source voltage ("V.sub.GS ") plotted on the "x" axis. The graphed function is increasingly linear for values of V.sub.GS substantially above a minimum voltage (labeled "V.sub.th " in FIG. 5), where the device is said to operate in "strong inversion." The threshold voltage of the device is often defined as the x-axis intercept of a tangent to the linear portion of the function. As shown in FIG. 5, such tangent intersects the x axis at the point labeled "V.sub.threshold-extrapolated " which is defined to be the effective threshold voltage for the purpose of calculating "I.sub.ds-major ", the majority carrier component. At values of V.sub.GS below V.sub.threshold-extrapolated, the device is said to be operating in "deep subthreshold" and I.sub.ds-major is typically negligible compared to I.sub.ds-minor. It is apparent from FIG. 5 that, in subthreshold, V.sub.GS can either be below V.sub.threshold-extrapolated (which is also equal to V.sub.FB +2.PHI..sub.b,) but above V.sub.FB, or, V.sub.GS can be equal to or slightly above V.sub.threshold-extrapolated, by as much as 100 mV or more.
For a typical NMOS transistor (whether or not its drain and gate are connected together), the logarithm of the channel current will be substantially proportional to the gate-to-source voltage V.sub.GS, for values of V.sub.GS above V.sub.threshold-extrapolated but below a transition voltage ("V.sub.strong-inversion " in FIG. 5). V.sub.strong-inversion is defined as (V.sub.threshold-extrapolated +.apprxeq.100 mV) At such values of V.sub.GS, the device is said to be operating in "near subthreshold." The logarithm of the channel current for said device when operating with a gate-to-source voltage greater than V.sub.FB but less than V.sub.threshold-extrapolated will be exponentially proportional to V.sub.GS and the device is said to be operating in "deep subthreshold."
As defined above, the "transconductance" of a MOSFET transistor is the change in the channel current in response to a unit change in gate-to-source voltage V.sub.GS. It is well known that the transconductance (g.sub.m) of a transistor operating in subthreshold is typically very high. This desirable characteristic of subthreshold operation could be exploited in a wide variety of applications if subthreshold operation could reliably be maintained. Although it had been known that MOSFETs (and other transistors) can exhibit in subthreshold a high level of transconductance g.sub.m, it had not been known how reliably to maintain a transconducting cell in subthreshold operation until the present invention.